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data sheet mos integrated circuit m pd17p709 4-bit single-chip microcontroller with built-in hardware dedicated to digital tuning systems the m pd17p709 is produced by replacing the built-in masked rom of the m pd17704 note , m pd17705 note , m pd17707 , m pd17708, and m pd17709 with a one-time prom. the m pd17p709 allows programs to be written once, so that the m pd17p709 is suitable for preproduction in m pd17704, m pd17705, m pd17707, m pd17708, or m pd17709 system development or low-volume production. when reading this document, also refer to the publications on the m pd17704, m pd17705, m pd17707, m pd17708, or m pd17709. note under development features ? compatible with the m pd17704, m pd17705, m pd17707, m pd17708, and m pd17709 ? built-in one-time prom : 32k bytes (16384 16 bits) ? supply voltage : v dd = 5 v 10% ordering information part number package m pd17p709gc-3b9 80-pin plastic qfp (14 14 mm, 0.65-mm pitch) document no. u10142ej2v0ds00 (2nd edition) date published november 1996 p printed in japan the mark shows major revised points. the information in this document is subject to change without notice. the electrical characteristics (including power supply currents) and pll analog characteristics of the m pd17p709 differ from those of the m pd17704, m pd17705, m pd17707, m pd17708, and m pd17709. in high-volume application set production, carefully check those differences. 1995
2 m pd17p709 program memory (rom) general-purpose data memory (ram) instruction execution time general-purpose ports stack level interrupt timers a/d converter d/a converter (pwm) serial interface pll intermediate frequency counter item (1/2) m pd17707 m pd17708 m pd17p709 16384 16 bits (masked rom) product function overview note under development 8192 16 bits 12288 16 bits (masked rom) (masked rom) 672 4 bits 1120 4 bits 1.78 m s (with 4.5-mhz crystal) i/o ports : 46 input ports : 12 output ports : 4 address stack : 15 levels interrupt stack : 4 levels dbf stack : 4 levels (operated by software) external : 6 (ce rising edge and int0 to int4) internal : 6 (timers 0 to 3, serial interfaces 0 and 1) 5 channels basic timer (clock: 10, 20, 50, 100 hz) : 1 channel 8-bit timer with gate counter (clock: 1 k, 2 k, 10 k, 100 khz) : 1 channel 8-bit timer (clock: 1 k, 2 k, 10 k, 100 khz) : 2 channels 8-bit timer, also used for pwm (clock: 440 hz, 4.4 khz) : 1 channel 8 bits 6 channels (hardware or software mode can be selected.) 3 channels (8-bit or 9-bit resolution, selected by software.) output frequency : 4.4 khz, 440 hz (8-bit pwm) 2.2 khz, 220 hz (9-bit pwm) 2 systems (3 channels) 3-wire serial i/o : 2 channels 2-wire serial i/o/i 2 c bus : 1 channel direct frequency division system (vcol pin (mf mode) : 0.5 to 3 mhz) pulse swallow system (vcol pin (hf mode) : 10 to 40 mhz) (vcoh pin (vhf mode) : 60 to 130 mhz) can be set to one of 13 frequencies (1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 18, 20, 25, or 50 khz). 2 error output pins (eo0 and eo1) unlock detection is enabled by software. intermediate frequency measurement p1c0/fmifc pin : 10 to 11 mhz in fmif mode 0.4 to 0.5 mhz in amif mode p1c1/amifc pin : 0.4 to 0.5 mhz in amif mode external gate width measurement p2a1/fcg1 and p2a0/fcg0 pins 16384 16 bits (one-time prom) 1776 4 bits frequency division system reference frequency charge pump phase comparator m pd17705 note m pd17704 note m pd17709
3 m pd17p709 (2/2) item product 2 output frequency : 1 khz, 3 khz, 4 khz, 6.7 khz (beep0 pin) 67 hz, 200 hz, 3 khz, 4 khz (beep1 pin) power-on reset (when the power is turned on) reset using the reset pin watchdog timer reset can be set only once at power-on: 65,536 instructions, 131,072 instructions, or non-use can be selected. stack pointer overflow/underflow reset can be set only once at power-on: the interrupt stack or address stack can be selected. ce reset (ce pin: low ? high) a ce reset delay timing can be set. power-failure detection function clock stop mode (stop) halt mode (halt) pll operation : v dd = 4.5 to 5.5 v cpu operation : v dd = 3.5 to 5.5 v 80-pin plastic qfp (14 14 mm, 0.65-mm pitch) beep output reset standby supply voltage package note under development m pd17704 note m pd17707 m pd17705 note m pd17708 m pd17709 m pd17p709
4 m pd17p709 pin configuration (top view) 80-pin plastic qfp (14 14 mm, 0.65-mm pitch) m pd17p709gc-3b9 (1) normal operation mode 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p0c2 p0c3 p2c0 p2c1 p2c2 p2c3 p3d0 p3d1 p3d2 p3d3 p3c0 p3c1 p3c2 p3c3 p2b0 p2b1 p2b2 p2b3 int0 int1 int2 p1a3/int4 p1a2/int3 p1a1 p1a0/tm0g p3a3 p3a2 p3a1 p3a0 p3b3 p3b2 p3b1 p3b0 p2a2 p2a1/fcg1 p2a0/fcg0 p1b3 p1b2/pwm2 p1b1/pwm1 p1b0/pwm0 gnd2 p0d3/ad3 p0d2/ad2 p0d1/ad1 p0d0/ad0 p1c3/ad5 p1c2/ad4 p1c1/amifc p1c0/fmifc v dd 1 vcoh vcol gnd1 eo0 eo1 test p1d3 p1d2 p1d1/beep1 p1d0/beep0 reset v dd 0 ce x in x out gnd0 reg p2d0 p2d1 p2d2 p0b0/si1 p0b1/so1 p0b2/sck1 p0b3/si0 p0a0/so0 p0a1/sck0 p0a2/scl p0a3/sda p0c0 p0c1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
5 m pd17p709 (2) prom programming mode note connect to the same potential as v dd . caution the parentheses above indicate the handling of the pins not used in prom programming mode. l : connect each pin to gnd through a resistor (470 ohms). h : connect each pin to v dd through a resistor (470 ohms). open : leave each pin open. 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 (l) (l) (open) md3 md2 md1 md0 v dd 1 gnd2 gnd1 (open) v pp (l) (l) (h) v dd 0 (l) clk (open) gnd0 reg note (l) d0 d1 d2 d3 d4 d5 d6 d7 (l) (l)
6 m pd17p709 pin names ad0-ad5 : a/d converter inputs amifc : am frequency counter input beep0, beep1 : beep outputs ce : chip enable clk : address update clock input d0-d7 : data i/o eo0, eo1 : error outputs fcg0, fcg1 : frequency counter gate inputs fmifc : fm frequency counter input gnd0-gnd2 : ground 0 to 2 int0-int4 : external interrupt inputs md0-md3 : operating mode selection pwm0-pwm2 : d/a converter outputs p0a0-p0a3 : port 0a p0b0-p0b3 : port 0b p0c0-p0c3 : port 0c p0d0-p0d3 : port 0d p1a0-p1a3 : port 1a p1b0-p1b3 : port 1b p1c0-p1c3 : port 1c p1d0-p1d3 : port 1d p2a0-p2a2 : port 2a p2b0-p2b3 : port 2b p2c0-p2c3 : port 2c p2d0-p2d2 : port 2d p3a0-p3a3 : port 3a p3b0-p3b3 : port 3b p3c0-p3c3 : port 3c p3d0-p3d3 : port 3d reg : cpu regulator reset : reset input sck0, sck1 : 3-wire serial clock i/o scl : 2-wire serial clock i/o sda : 2-wire serial data i/o si0, si1 : 3-wire serial data input so0, so1 : 3-wire serial data output test : test input tm0g : timer 0 gate input vcoh : local oscillation high input vcol : local oscillation low input v dd 0, v dd 1 : power supply v pp : program voltage application x in , x out : main clock oscillation
7 m pd17p709 block diagram remark pins enclosed in parentheses are used in prom programming mode. 4 4 4 4 4 4 4 4 3 4 4 3 4 4 4 4 p0a0-p0a3 vcoh vcol eo0 eo1 so0/p0a0 sck0/p0a1 scl/p0a2 sda/p0a3 si0/p0b3 sck1/p0b2 so1/p0b1 si1/p0b0 int0 int1 int2 int3/p1a2 int4/p1a3 fcg0/p2a0 fcg1/p2a1 fmifc/p1c0 amifc/p1c1 ce reset x in (clk) x out v dd 0,v dd 1 reg v cpu peripheral cpu tm0g/p1a0 beep0/p1d0 beep1/p1d1 p0b0-p0b3 p0c0-p0c3 p0d0-p0d3 p1a0-p1a3 p1b0-p1b3 p1c0(md0)- p1c3(md3) p1d0-p1d3 p2a0-p2a2 p2b0-p2b3 p2c0(d0)-p2c3(d3) p3a0-p3a3 p3b0-p3b3 p3c0-p3c3 ad0/p0d0 ad1/p0d1 ad2/p0d2 ad3/p0d3 ad4/p1c2 ad5/p1c3 pwm0/p1b0 pwm1/p1b1 pwm2/p1b2 gnd0-gnd2 p3d0(d4)-p3d3(d7) p2d0-p2d2 ports rf alu sysreg ram 1776 4 bits instruction decoder one-time prom 16384 16 bits program counter stack a/d converter d/a converter 8-bit timer 3 basic timer pll serial interface 0 serial interface 1 beep interrupt control frequency counter 8-bit timer 0 8-bit timer 1 8-bit timer 2 osc reset regurator gate counter
8 m pd17p709 contents 1. pin functions ......................................................................................................................... 9 1.1 normal operation mode ....................................................................................................... 9 1.2 prom programming mode ..................................................................................................... 13 1.3 equivalent circuit of pins .................................................................................................. 14 1.4 handling unused pins ............................................................................................................ 19 1.5 notes on use of the ce, int0-int4, and reset pins (only in normal operation mode) ....................................................................................................................... 21 1.6 notes on use of the test pin (only in normal operation mode) ...................... 21 2. one-time prom (program memory) write, read, and verification ................ 22 2.1 operating modes for program memory write, read, and verification ........ 23 2.2 program memory write procedure ............................................................................... 24 2.3 program memory read procedure ................................................................................. 25 3. electrical characteristics .......................................................................................... 26 4. package drawing ................................................................................................................ 31 5. recommended soldering conditions ....................................................................... 32 appendix development tools .............................................................................................. 33
9 m pd17p709 power-on reset wdt&sp reset ce reset input (p1a3-p1a0) input (p1a3-p1a0) held held when reset when the clock is stopped power-on reset wdt&sp reset ce reset held held when reset when the clock is stopped 1. pin functions 1.1 normal operation mode input input int2 int1 int0 p1a3/int4 p1a2/int3 p1a1 p1a0/tm0g p3a3 to p3a0 p3b3 to p3b0 p2a2 p2a1/fcg1 p2a0/fcg0 1 41 42 2 3 4 5 6 to 9 10 to 13 14 15 16 input for edge-detected vectored. either a rising edge or falling edge can be selected. input for port 1a, external interrupt request signal, and event signal p1a3-p1a0 4-bit input port int4, int3 edge-detected vectored interrupt tm0g gate input for 8-bit timer 0 4-bit i/o port. input/output can be specified in 4-bit units. 4-bit i/o port. input/output can be specified in 4-bit units. input for port 2a and external gate counter p2a2-p2a0 3-bit i/o port input/output can be specified bit by bit. fcg1, fcg0 external gate counter input ? ? cmos push-pull cmos push-pull cmos push-pull power-on reset wdt&sp reset ce reset input input held held when reset when the clock is stopped power-on reset wdt&sp reset ce reset input (p2a2-p2a0) input (p2a2-p2a0) held (p2a2-p2a0) when reset when the clock is stopped held (p2a2-p2a0) symbol output format function pin no.
10 m pd17p709 17 18 to 20 21 33 75 22 to 25 26 27 28 29 p1b3 p1b2/pwm2 to p1b0/pwm0 gnd2 gnd1 gnd0 p0d3/ad3 to p0d0/ad0 p1c3/ad5 p1c2/ad4 p1c1/amifc p1c0/fmifc output format power-on reset wdt&sp reset ce reset low-level output (p1b3-p1b0) when reset when the clock is stopped n-ch open-drain (12-v withstand voltage) ? ? ? low-level output (p1b3-p1b0) power-on reset wdt&sp reset ce reset held held when reset when the clock is stopped output for port 1b and d/a converter p1b3-p1b0 4-bit output port pwm2-pwm0 8-bit or 9-bit d/a converter output ground input for port 0d and a/d converter p0d3-p0d0 4-bit input port a pull-down resistor can be set bit by bit. ad3-ad0 analog input for 8-bit-resolution a/d converter input for port 1c, a/d converter, and if counter p1c3-p1c0 4-bit input port ad5, ad4 analog input for 8-bit-resolution a/d converter fmifc, amifc frequency counter input input (p1c3-p1c0) input (p1c3-p1c0) when reset when the clock is stopped input with pull- down resistors (p0d3-p0d0) input with pull- down resistors (p0d3-p0d0) symbol function held (p1b3-p1b0) held p1c3/ad5, p1c2/ad4 held p1c1/amifc, p1c0/fmifc input (p1c1, p1c0) ce reset wdt&sp reset power-on reset p1c3/ad5, p1c2/ad4 held p1c1/amifc, p1c0/fmifc input (p1c1, p1c0) pin no.
11 m pd17p709 v dd 1 v dd 0 vcoh vcol eo0 eo1 test p1d3 p1d2 p1d1/beep1 p1d0/beep0 p2b3 to p2b0 p3c3 to p3c0 function when reset when the clock is stopped 30 79 31 32 34 35 36 37 38 39 40 43 to 46 47 to 50 power-on reset when reset when the clock is stopped high-impedance output high-impedance output high-impedance output ce reset input (p1d3-p1d0) input (p1d3-p1d0) held (p1d3-p1d0) held (p1d3-p1d0) wdt&sp reset wdt&sp reset power-on reset held held when reset when the clock is stopped ce reset wdt&sp reset input input power supply. apply the same voltage to the v dd 1 and v dd 0 pins. when the cpu and peripheral functions are operating: 4.5 to 5.5 v when only the cpu is operating: 3.5 to 5.5 v when the clock is stopped: 2.2 to 5.5 v input for pll local oscillation (vco) frequency vcoh active when vhf mode is selected by software. otherwise, pulled down. vcol active when hf or mw mode is selected by software. otherwise, pulled down. inputs to these pins are to be ac-amplified. cut, therefore, the dc components in the input signals by using capacitors. output from the charge pump of the pll frequency synthesizer. the result of phase comparison between the divided local oscillation fre- quency and reference frequency is output. test input pin. be sure to connect it to gnd. output for port 1d and beep p1d3-p1d0 4-bit i/o port input/output can be specified bit by bit. beep1, beep0 beep output 4-bit i/o port. input/output can be specified bit by bit. 4-bit i/o port. input/output can be specified in 4-bit units. power-on reset wdt&sp reset ce reset held held when reset when the clock is stopped input input ? ? cmos tristate ? cmos push-pull cmos push-pull cmos push-pull symbol pin no. output format power-on reset high-impedance output ce reset
12 m pd17p709 pin no. cmos push-pull cmos push-pull cmos push-pull n-ch open-drain cmos push-pull cmos push-pull output format 51 to 54 55 to 58 59 to 62 63 64 65 66 67 68 69 70 71 to 73 power-on reset wdt&sp reset ce reset input input held held when reset when the clock is stopped power-on reset wdt&sp reset ce reset input input held held when reset when the clock is stopped power-on reset wdt&sp reset ce reset input input held held when reset when the clock is stopped power-on reset wdt&sp reset ce reset when reset when the clock is stopped power-on reset wdt&sp reset ce reset input input held held when reset when the clock is stopped 4-bit i/o port. input/output can be specified in 4-bit units. 4-bit i/o port. input/output can be specified bit by bit. 4-bit i/o port. input/output can be specified bit by bit. input/output for p0a or p0b and serial interface p0a3-p0a0 4-bit i/o port input/output can be specified bit by bit. p0b3-p0b0 4-bit i/o port input/output can be specified bit by bit. sda, scl serial data and serial clock i/o when the 2-wire serial i/o or i 2 c bus of serial interface 0 is selected. sck0, so0, si0 serial clock i/o, serial data output, and serial data input when the 3-wire serial i/o of serial interface 0 is selected. sck1, so1, si1 serial clock i/o, serial data output, and serial data input when the 3-wire serial i/o of serial interface 1 is selected. 3-bit i/o port. input/output can be specified bit by bit. p3d3 to p3d0 p2c3 to p2c0 p0c3 to p0c0 p0a3/sda p0a2/scl p0a1/sck0 p0a0/so0 p0b3/si0 p0b2/sck1 p0b1/so1 p0b0/si1 p2d2 to p2d0 input p0a3-p0a0 p0b3-p0b0 input p0a3-p0a0 p0b3-p0b0 held p0a3-p0a0 p0b3-p0b0 held p0a3-p0a0 p0b3-p0b0 symbol function
13 m pd17p709 74 76 77 78 80 reg x out x in ce reset ? ? ? ? output format cpu regulator. use 0.1- m f capacitor to connect it to gnd. a crystal is connected to these pins. input for device operation selection, ce reset, and interrupt signals device operation selection when ce is high, the pll frequency synthesizer can be operated. when ce is low, the pll frequency synthesizer is automatically disabled by the device. ce reset setting ce from low to high resets the device upon the detection of a rising edge of the internal basic timer setting pulse. a reset timing delay can also be specified. interrupt a vectored interrupt occurs upon the detection of a falling edge of the input signal. reset input pin no. symbol function 1.2 prom programming mode remark the pins other than those listed above are not used in prom programming mode. for the handling of the unused pins, see pin configuration , (2) prom programming mode . pin no. symbol 26 to 29 21 33 75 36 30 79 51 to 58 77 md3 to md0 gnd2 gnd1 gnd0 v pp v dd 1 v dd 0 d7 to d0 clk input for operating mode selection for program memory write, read, or verification ground pin to which program voltage is applied during program memory write, read, or verification. +12.5 v is applied. power supply pins. +6 v is applied during program memory write, read, or verification. 8-bit data i/o for program memory write, read, or verification clock input for address updating during program memory write, read, or verification output format function ? ? ? ? cmos push-pull ?
14 m pd17p709 1.3 equivalent circuit of pins (1) p0a (p0a1/sck0, p0a0/so0) p0b (p0b3/si0, p0b2/sck1, p0b1/so1, p0b0/si1) p0c (p0c3, p0c2, p0c1, p0c0) p1d (p1d3, p1d2, p1d1/beep1, p1d0/beep0) p2a (p2a2, p2a1/fcg1, p2a0/fcg0) p2b (p2b3, p2b2, p2b1, p2b0) p2c (p2c3, p2c2, p2c1, p2c0) p2d (p2d2, p2d1, p2d0) p3a (p3a3, p3a2, p3a1, p3a0) p3b (p3b3, p3b2, p3b1, p3b0) p3c (p3c3, p3b2, p3c1, p3c0) p3d (p3d3, p3d2, p3d1, p3d0) note in this circuit, a current drained by noise does not increase even if the circuit is in the floating state, because of the internal signal being output when the clock stop instruction is executed. v dd v dd ckstop note (i/o)
15 m pd17p709 (2) p0a (p0a3/sda, p0a2/scl) (i/o) note in this circuit, a current drained by noise does not increase even if the circuit is in the floating state, because of the internal signal being output when the clock stop instruction is executed. (3) p1b (p1b3, p1b2/pwm2, p1b1/pwm1, p1b0/pwm0) (output) (4) p0d (p0d3/ad3, p0d2/ad2, p0d1/ad1, p0d0/ad0) (input) note in this circuit, a current drained by noise does not increase even if the circuit is in the floating state, because of the internal signal being output when the clock stop instruction is executed. v dd ckstop note v dd ckstop note a/d converter p0dpld flag high on-state resistor
16 m pd17p709 (5) p1a (p1a1) (input) (6) p1c (p1c3/ad5, p1c2/ad4) (input) (7) p1c (p1c1/amifc, p1c0/fmifc) (input) v dd v dd a/d converter v dd v dd v dd general-purpose port high on-state resistor frequency counter
17 m pd17p709 (8) ce reset int0, int1, int2 p1a (p1a3/int4, p1a2/int3, p1a0/tm0g) (9) x out (output), x in (input) (10) eo1, eo0 (output) v dd v dd dwn up (schmitt-triggered input) v dd v dd high on-state resistor high on-state resistor x in x out internal clock
18 m pd17p709 (11) vcoh, vcol (input) v dd v dd high on-state resistor high on-state resistor
19 m pd17p709 1.4 handling unused pins the unused pins should be handled as indicated in table 1-1. table 1-1 handling unused pins notes 1. when making an external connection to v dd with a pull-up resistor, or to gnd with a pull-down resistor, note the following: if the resistance of the pull-up or pull-down resistor is too high, the pin approaches the high impedance state, thus increasing the through current drawn by the port. in general, pull-up and pull-down resistors should have a resistance of between 20 and 50 kilohms, depending on the application circuit. 2. do not specify amifc or fmifc. if amifc or fmifc is specified, current drain increases. 3. i/o ports become general-purpose input ports upon power-on reset, reset by the reset pin, watchdog timer reset, or stack overflow/underflow reset. input n-ch open-drain output i/o note 3 connect each pin to gnd through a resistor. note 1 specify as a port and connect each pin to v dd or gnd through a resistor. note 1 connect each pin to gnd through a resistor. note 1 specify low output, in the software, and leave open. specify as a general-purpose input port, in the software, and connect each pin to v dd or gnd through a resistor. note 1 port pins pin i/o format recommended handling (1/2) p0d3/ad3-p0d0/ad0 p1c3/ad5 p1c2/ad4 p1c1/amifc note 2 p1c0/fmifc note 2 p1a3/int4 p1a2/int3 p1a1 p1a0/tm0g p1b3 p1b2/pwm2-p1b0/pwm0 p0a3/sda p0a2/scl p0a1/sck0 p0a0/so0 p0b3/si0 p0b2/sck1 p0b1/so1 p0b0/si1 p0c3-p0c0 p1d3 p1d2 p1d1/beep1 p1d0/beep0 p2a2 p2a1/fcg1 p2a0/fcg0 p2b3-p2b0 p2c3-p2c0 p2d2-p2d0
20 m pd17p709 (2/2) i/o note 2 input output input input ? input p3a3-p3a0 p3b3-p3b0 p3c3-p3c0 p3d3-p3d0 ce eo1 eo0 int0-int2 reset test vcoh vcol pin i/o format recommended handling specify as a general-purpose input port, in the software, and connect each pin to v dd or gnd through a resistor. note 1 connect to v dd through a resistor. note 1 leave each pin open. connect each pin to gnd through a resistor. note 1 connect to v dd through a resistor. note 1 connect directly to gnd. disable pll, in the program, and leave each pin open. port pins notes 1. when making an external connection to v dd with a pull-up resistor, or to gnd with a pull-down resistor, note the following: if the resistance of the pull-up or pull-down resistor is too high, the pin approaches the high impedance state, thus increasing the through current drawn by the port. in general, pull-up and pull-down resistors should have a resistance of between 20 and 50 kilohms, depending on the application circuit. 2. i/o ports become general-purpose input ports upon power-on reset, reset by the reset pin, watchdog timer reset, or stack overflow/underflow reset. other than port pins
21 m pd17p709 1.5 notes on use of the ce, int0-int4, and reset pins (only in normal operation mode) the ce, int0-int4, and reset pins can be used as the test mode selection pin for testing the internal operation of the m pd17p709 (ic test), besides the usage shown in section 1.1 . applying a voltage exceeding v dd to the ce, int0-int4, or reset pin causes the m pd17p709 to enter test mode. when noise exceeding v dd comes in during normal operation, the device may not operate normally. for example, if the wiring from the ce, int0-int4, or reset pin is too long, noise may be induced on the wiring, causing this mode switching. when installing the wiring, lay the wiring in such a way that noise is suppressed as much as possible. if noise yet arises, use an external part to suppress it as shown below. connect a diode with low v f between the pin connect a capacitor between the pin and v dd . and v dd . 1.6 notes on use of the test pin (only in normal operation mode) applying v dd to the test pin causes the m pd17p709 to enter test mode or program memory write/verify mode. keep the wiring as short as possible and connect the test pin directly to the gnd pin. when the wiring between the test pin and gnd pin is too long or external noise enters the test pin, a voltage difference may occur between the test pin and gnd pin. when this happens, your program may malfunction. v dd ce, int0-int4, reset v dd diode with low v f ce, int0-int4, reset v dd v dd gnd test keep the wiring as short as possible.
22 m pd17p709 2. one-time prom (program memory) write, read, and verification the program memory built into the m pd17p709 is a one-time prom (16384 16 bits) that is electrically writable. in normal operation, this prom is accessed on a 16-bit word basis. during program memory write, read, and verification, the prom is accessed on an 8-bit word basis. the higher 8 bits of a 16-bit word are located at an even- numbered address, and the lower 8 bits are located at an odd-numbered address. for prom write, read, and verification, prom programming mode must be specified, and the pins listed in table 2-1 are used. in this case, address input is not used. instead, clock input on the clk pin is used to update addresses. table 2-1 pins used for program memory write, read, and verification for writing to the built-in prom, a specified prom programmer and dedicated programmer adapter are to be used. the following prom programmers and programmer adapters are usable: third-party prom programmers are also available: for example, af-9703, af-9704, af-9705, and af-9706 (manufactured by ando electric co., ltd.) pin used to apply the program voltage (+12.5 v) used to apply an address update clock used to select an operating mode used to input/output 8-bit data used to apply the power supply voltage (+6 v) v pp clk md0-md3 d0-d7 v dd 0, v dd 1 function pg-1500 + pa-17kdz (adapter for pg-1500) programmer adapter prom programmer pa-17p709gc
23 m pd17p709 fig. 2-1 pa17p709gc and pa-17kdz 2.1 operating modes for program memory write, read, and verification the m pd17p709 is placed in program memory write, read, and verify mode when +6 v is applied to the v dd pin, and +12.5 v to the v pp pin. in this mode, one of the operating modes indicated in table 2-2 is set, depending on the setting of the md0 to md3 pins. the input pins that are not used for program memory write, read, and verification are connected to gnd through a pull-down resistor (470 ohms). (see pin configuration , (2) prom programming mode .) table 2-2 operating modes for program memory write, read, and verication remark x: l or h operating mode specification md0 h l l h v dd v pp operating mode md2 h h h h md1 l h l x md3 l h h h program memory address zero-clear mode write mode read/verify mode program inhibit mode +12.5v +6v pa-17kdz pa-17p709gc to pg-1500
24 m pd17p709 2.2 program memory write procedure the program memory write procedure is described below. the procedure allows high-speed write operation. (1) connect the unused pins to gnd through pull-down resistors. the clk pin must be low. (2) apply 5 v to the v dd pin. the v pp pin must be low. (3) apply 5 v to the v pp pin after waiting 10 m s. (4) specify program memory address zero-clear mode, using the mode setting pins. (5) apply 6 v to v dd , and 12.5 v to v pp . (6) program inhibit mode (7) write data in 1-ms write mode. (8) program inhibit mode (9) verify mode. when data has been written normally, proceed to step (10). when data has not been written normally, repeat steps (7) to (9). (10) perform an additional write operation ((x: number of write operations performed in steps (7) to (9)) 1 ms). (11) program inhibit mode (12) apply four pulses to the clk pin to increment the program memory address by 1. (13) repeat steps (7) to (12) until the last address is reached. (14) program memory address zero-clear mode (15) change the voltage applied to the v dd and v pp pins to 5 v. (16) turn off the power. steps (2) to (12) are illustrated below. repeat x times reset write verify additional write address increment data input data output data input v dd + 1 v dd v dd gnd v pp v dd gnd v pp clk d0-d7 md0 md1 md2 md3 hi-z hi-z hi-z hi-z
25 m pd17p709 2.3 program memory read procedure (1) connect the unused pins to gnd through pull-down resistors. the clk pin must be low. (2) apply 5 v to the v dd pin. the v pp pin must be low. (3) apply 5 v to the v pp pin after waiting 10 m s. (4) specify program memory address zero-clear mode, using the mode setting pins. (5) apply 6 v to v dd , and 12.5 v to v pp . (6) program inhibit mode (7) verify mode. when a clock pulse signal is applied to the clk pin, data is output for each address every four clock pulses. (8) program inhibit mode (9) program memory address zero-clear mode (10) change the voltage applied to the v dd and v pp pins to 5 v. (11) turn off the power. steps (2) to (9) are illustrated below. v dd + 1 v dd gnd v pp v dd gnd clk d0-d7 md0 md1 md2 md3 v dd v pp hi-z hi-z data output data output l reset
26 m pd17p709 parameter unit v dd v pp v i v o i oh i ol v bds p t t a t stg symbol v v v v v ma ma ma ma ma ma ma ma v mw c c supply voltage v v parameter condition unit 4.5 3.5 min. 5.0 5.0 typ. 5.5 5.5 max. v dd1 v dd2 symbol while the cpu and pll are operating while the cpu is operating but the pll is halted output withstand voltage v parameter condition unit min. typ. 12 max. v bds symbol p1b0-p1b3 condition rating 3. electrical characteristics absolute maximum ratings (t a = 25 c) caution absolute maximum ratings are rated values beyond which physical damage will be caused to the product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. always use the product within its rated values. recommended operating ranges (t a = e40 to +85 c) recommended output withstand voltage (t a = e40 to +85 c) at other than ce, int0-int4, and reset pins ce, int0-int4, and reset pins at other than p1b0-p1b3 at one pin total for p2a0-p2a2, p3a0-p3a3, and p3b0-p3b3 total for p0a0-p0a3, p0b0-p0b3, p0c0-p0c3, p1d0-p1d3, p2b0-p2b3, p2c0-p2c3, p2d0-p2d2, p3c0-p3c3, and p3d0-p3d3 at one pin of p1b0-p1b3 at one pin of other than p1b0-p1b3 total for p2a0-p2a2, p3a0-p3a3, and p3b0-p3b3 total for p0a0-p0a3, p0b0-p0b3, p0c0-p0c3, p1d0-p1d3, p2b0-p2b3, p2c0-p2c3, p2d0-p2d2, p3c0-p3c3, and p3d0-p3d3 total for p1b0-p1b3 p1b0-p1b3 e0.3 to +6.0 e0.3 to +13.5 e0.3 to v dd + 0.3 e0.3 to v dd + 0.6 e0.3 to v dd + 0.3 e8.0 e15.0 e25.0 12.0 8.0 15.0 25.0 25.0 14.0 200 e40 to +85 e55 to +125 supply voltage prom program voltage input voltage output voltage high output current low output current output withstand voltage total loss operating ambient temperature storage temperature
27 m pd17p709 dc characteristics (t a = e40 to +85 c, v dd = 3.5 to 5.5 v) parameter condition symbol unit max. typ. min. 3.5 2.2 2.0 0.7v dd 0.8v dd 0.55v dd 0 0 0 e1.0 e3.0 1.0 3.0 7.0 5.0 1.5 0.7 2.0 2.0 3.0 1.5 5.5 5.5 5.5 4.0 30.0 v dd v dd v dd 0.3v dd 0.2v dd 0.15v dd 150 1.0 1.0 1.0 e1.0 ma ma v v v m a m a v v v v v v ma ma ma ma ma m a m a m a m a m a supply current data hold voltage data hold current high input voltage low input voltage high output current low output current high input current output-off leakage current high input leakage current low input leakage current the timer flip-flop is used for detecting power failure. data memory contents are held. v dd = 5 v, t a = 25 c i dd1 i dd2 v ddr1 v ddr2 v ddr3 i ddr1 i ddr2 v ih1 v ih2 v ih3 v il1 v il2 v il3 i oh1 i oh2 i ol1 i ol2 i ol3 i ih i lo1 i lo2 i lih i lil the cpu is operating but the pll is halted, with a sinusoidal wave applied to the x in pin. (f in = 4.5 mhz 1%, v in = v dd ) the cpu and pll are halted, with a sinusoidal wave applied to the x in pin. (f in = 4.5 mhz 1%, v in = v dd ) the halt instruction is used. the crystal oscillator is operating. the crystal oscillator is halted. the crystal oscillator is halted. p0a0, p0b1, p0c0-p0c3, p1a0, p1a1, p1c0-p1c3, p1d0-p1d3, p2a2, p2b0-p2b3, p2c0-p2c3, p2d0-p2d2, p3a0-p3a3, p3b0-p3b3, p3c0-p3c3, p3d0-p3d3 p0a1-p0a3, p0b0, p0b2, p0b3, p2a0, p2a1, ce, int0-int4, reset p0d0-p0d3 p0a0, p0b1, p0c0-p0c3, p1a0, p1a1,p1c0-p1c3, p1d0-p1d3, p2a2, p2b0-p2b3, p2c0-p2c3, p2d0-p2d2, p3a0-p3a3, p3b0-p3b3, p3c0-p3c3, p3d0-p3d3 p0a1-p0a3, p0b0, p0b2, p0b3, p2a0, p2a1, ce, int0-int4, reset p0d0-p0d3 p0a0-p0a3, p0b0-p0b3, p0c0-p0c3, p1d0-p1d3, p2a0-p2a2, p2b0-p2b3, p2c0-p2c3, p2d0-p2d2, p3a0-p3a3, p3b0-p3b3, p3c0-p3c3, p3d0-p3d3 v oh = v dd e 1 v eo0, eo1 v dd = 4.5 to 5.5 v, v oh = v dd e 1 v p0a0-p0a3, p0b0-p0b3, p0c0-p0c3, p1d0-p1d3, p2a0-p2a2, p2b0-p2b3, p2c0-p2c3, p2d0-p2d2, p3a0-p3a3, p3b0-p3b3, p3c0-p3c3, p3d0-p3d3 v ol = 1 v eo0, eo1 v dd = 4.5 to 5.5 v, v ol = 1 v p1b0-p1b3 v ol = 1 v p0d0-p0d3 are pulled down. v in = v dd p1b0-p1b3 v in = 12 v eo0, eo1 v in = v dd , v in = 0 v input pin v in = v dd input pin v in = 0 v
28 m pd17p709 ac characteristics (t a = e40 to +85 c, v dd = 5 v 10%) note the condition of sinusoidal wave input v in = 0.1v p-p is the rated value when the m pd17p709 alone is operating. where influence of noise must be taken into consideration, operation under input amplitude condition of v in = 0.15v p-p is recommended. a/d converter characteristics (t a = e40 to +85 c, v dd = 5 v 10%) reference characteristics (t a = +25 c, v dd = 5.0 v) parameter condition unit max. typ. min. 0.8 0.5 10 60 0.4 10 0.4 3 3 40 130 0.5 11 0.5 1 0.7 mhz mhz mhz mhz mhz mhz mhz mhz mhz operating frequency sio0 input frequency sio1 input frequency symbol f in1 f in2 f in3 f in4 f in5 f in6 f in7 f in8 parameter condition typ. min. unit max. lsb lsb total error in a/d conversion total error in a/d conversion 8 bits 8 bits t a = 0 to 85 c 3.0 2.5 symbol parameter condition typ. min. unit max. ma supply current the cpu and pll are operating, with a sinusoidal wave applied to the vcoh pin. (f in = 130 mhz, v in = 0.3v p-p ) 12.0 6.0 symbol vcol pin in mf mode vcol pin in hf mode, with a sinusoidal wave applied to the v in pin = 0.1v p-p note vcoh pin in vhf mode, with a sinusoidal wave applied to the v in pin = 0.1v p-p note amifc pin, with a sinusoidal wave applied to the v in pin = 0.15v p-p fmifc pin in fmif count mode, with a sinusoidal wave applied to the v in pin = 0.20v p-p fmifc pin in amif count mode, with a sinusoidal wave applied to the v in pin = 0.15v p-p external clock external clock sinusoidal wave applied to the v in pin = 0.15v p-p sinusoidal wave applied to the v in pin = 0.20v p-p i dd3
29 m pd17p709 dc programming characteristics (t a = 25 c, v dd = 6.0 0.25 v, v pp = 12.5 0.5 v) cautions 1. v pp must be under +13.5 v including overshoot. 2. v dd must be applied before v pp on and must be off after v pp off. ac programming characteristics (t a = 25 c, v dd = 6.0 0.25 v, v pp = 12.5 0.5 v) notes 1. symbols used for the m pd27c256 (the m pd27c256 is used only for maintenance.) 2. the internal address signal is incremented by 1 on the falling edge of the third clock (clk) pulse, with four clk pulses treated as one cycle. internal addresses are not connected to pins. parameter input high voltage input low voltage input leakage current output high voltage output low voltage v dd supply current v pp supply current condition other than clk clk other than clk clk v in = v il or v ih i oh = e1 ma i ol = 1 ma md0 = v il , md1 = v ih min. 0.7v dd v dd e 0.5 0 0 v dd e 1.0 typ. max. v dd v dd 0.2v dd 0.4 10 1.0 30 30 unit v v v v m a v v ma ma v ih1 v ih2 v il1 v il2 i li v oh v ol i dd i pp symbol parameter symbol note 1 min. typ. max. unit 130 1.05 21.0 1 4.19 2 130 2 m s m s m s m s m s ns m s m s ms ms m s m s m s m s m s m s mhz m s m s m s m s m s ns m s m s m s 1.0 condition md0 = md1 = v il t m1h + t m1r 3 50 m s when reading program memory 2 2 2 2 2 0 2 2 0.95 0.95 2 2 2 10 0.125 2 2 2 2 0 2 10 address setup time note 2 (referred to md0 ) md1 setup time (referred to md0 ) data setup time (referred to md0 ) address hold time note 2 (referred to md0 - ) data hold time (referred to md0 - ) data output float delay from md0 - v pp setup time (referred to md3 -) v dd setup time (referred to md3 -) initial program pulse width additional program pulse width md0 setup time (referred to md1 -) data output delay from md0 md1 hold time (referred to md0 - ) md1 recovery time (referred to md0 ) program counter reset time clk input high, low level range clk input frequency initial mode set time md3 setup time (referred to md1 -) md3 hold time (referred to md1 ) md3 setup time (referred to md0 ) data output delay from address increment note 2 data output hold time from address increment note 2 md3 hold time (referred to md0 - ) data output float delay from md3 reset setup time t as t m1s t ds t ah t dh t df t vps t vds t pw t opw t m0s t dv t m1h t m1r t pcr t xh ,t xl f x t i t m3s t m3h t m3sr t dad t had t m3hr t dfr t res t as t oes t ds t ah t dh t df t vps t vcs t pw t opw t ces t dv t oeh t or ? ? ? ? ? ? ? t acc t oh ? ? ?
30 m pd17p709 write program memory timing remark the dashed line indicates high-impedance. read program memory timing v pp v dd gnd v dd + 1 v dd gnd clk d0-d7 md0 md1 md2 md3 v pp v dd hi-z hi-z data output data output l t res t vps t vds t xh t xl t dad t had t dv t dfr t m3hr t i t pcr t m3sr data input data output data input data input t res t vps t vds t i t ds t dh t dv t df t ds t dh t ah t as t pw t m1r t m0s t opw t pcr t m1s t m1h t m3s t m3h t xh t xl v pp v dd gnd v dd + 1 v dd gnd clk d0-d7 md0 md1 md2 md3 v pp v dd
31 m pd17p709 4. package drawing 80 pin plastic qfp (14 14) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. l 0.8 0.2 0.031 +0.009 e0.008 m 0.15 0.006 n 0.10 0.004 p 2.7 0.106 a 17.2 0.4 0.677 0.016 b 14.0 0.2 0.551 +0.009 e0.008 c 14.0 0.2 0.551 +0.009 e0.008 d 17.2 0.4 0.677 0.016 f 0.825 0.032 g 0.825 0.032 h 0.30 0.10 0.012 +0.004 e0.005 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) q 0.1 0.1 0.004 0.004 r5 5 5 5 +0.10 e0.05 +0.004 e0.003 m m l k j h q p n r detail of lead end i g k 1.6 0.2 0.063 0.008 60 61 40 80 1 21 20 41 a b cd f s s80gc-65-3b9-4 s 3.0 max. 0.119 max.
32 m pd17p709 soldering process recommended conditions soldering conditions infrared ray reflow vps wave soldering partial heating method ir35-00-2 vp15-00-2 ws60-00-1 ? 5. recommended soldering conditions the conditions listed below shall be met when soldering the m pd17p709. for details of the recommended soldering conditions, refer to our document smd surface mount technology manual (c10535e). please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. table 5-1 soldering conditions for surface-mount devices m pd17p709gc-3b9: 80-pin plastic qfp (14 14 mm, 0.65-mm pitch) caution do not apply more than a single process at once, except for partial heating method. peak package's surface temperature: 235 c reflow time: 30 seconds or less (at 210 c or more) maximum allowable number of reflow processes: 2 peak package's surface temperature: 215 c reflow time: 40 seconds or less (at 200 c or more) maximum allowable number of reflow processes: 2 solder temperature: 260 c or less flow time: 10 seconds or less number of flow processes: 1 preheating temperature: 120 c max. (measured on the package surface) terminal temperature: 300 c or less heat time: 3 seconds or less (for one side of a device)
33 m pd17p709 name description appendix development tools the following support tools are available for developing programs for the m pd17p709. hardware in-circuit emulator ie-17k ie-17k-et note 1 emu-17k note 2 se board (se-17709) emulation probe (ep-17k80gc) conversion socket (ev-9200gc-80 note 3 ) prom programmer (pg-1500) programmer adapter (pa-17p709gc) the ie-17k, ie-17k-et, and emu-17k are in-circuit emulators applicable to the 17k series. the ie-17k and ie-17k-et are connected to the host machine (pc-9800 series or ibm pc/ at tm ) through the rs-232c interface. the emu-17k is inserted into the extension slot of the host machine (pc-9800 series). use the system evaluation board (se board) corresponding to each product together with one of these in-circuit emulators. simplehost tm , a man machine interface, implements an advanced debug environment. the emu-17k also enables user to check the contents of the data memory in real time. the se-17709 is an se board for the m pd17709 sub-series. it is used alone for evaluating the system. it is also used for debugging, in combination with an in-circuit emulator. the ep-17k80gc is an emulation probe for the m pd17p709gc. when used with the ev- 9200gc-80 note 3 , this emulation probe connects the se board to the target system. the ev-9200gc-80 is a conversion socket for the 80-pin plastic qfp (14 14 mm). it is used to connect the ep-17k80gc to the target system. the pg-1500 is a prom programmer for the m pd17p709. use this prom programmer with the pa-17kdz (adapter for the pg-1500) and pa- 17p709gc programmer adapter, to program the m pd17p709. the pa-17p709gc is a socket unit for the m pd17p709. it is used with the pg-1500. notes 1. low-end model, operating on an external power supply 2. the emu-17k is a product of i.c corporation. contact i.c corporation (tokyo, 03-3733-1163) for details. 3. the ep-17k80gc is supplied together with one ev-9200gc-80. a set of five ev-9200gc-80s is also available. remark third-party prom programmers are also available: for example, af-9703, af-9704, af-9705, and af- 9706 (manufactured by ando electric co., ltd.). these prom programmers can be used with the pa- 17p709gc programmer adapter. for details, contact ando electric co., ltd. (tokyo, 03-3733-1151).
34 m pd17p709 17k series assembler (as17k) device file (as17704) support software ( simplehost ) as17k is an assembler applicable to the 17k series. in developing m pd17p709 programs, as17k is used in combination with a device file (as17704). as17704 has a device file for the m pd17p709 . it is used together with the assembler (as17k), which is applicable to the 17k series. simplehost , running under windows tm , provides a man machine interface in develop- ing programs by using a personal computer and in- circuit emulator. os part number description distribution media host machine software pc-9800 series ibm pc/at pc-9800 series ibm pc/at pc-9800 series ibm pc/at name ms-dos pc dos windows ms-dos tm pc dos tm ms-dos pc dos m s5a10as17k m s5a13as17k m s7b10as17k m s7b13as17k m s5a10as17704 m s5a13as17704 m s7b10as17704 m s7b13as17704 m s5a10ie17k m s5a13ie17k m s7b10ie17k m s7b13ie17k 5.25-inch, 2hd 3.5-inch, 2hd 5.25-inch, 2hc 3.5-inch, 2hc 5.25-inch, 2hd 3.5-inch, 2hd 5.25-inch, 2hc 3.5-inch, 2hc 5.25-inch, 2hd 3.5-inch, 2hd 5.25-inch, 2hc 3.5-inch, 2hc remark the following table lists the versions of the operating systems described in the above table. os versions ms-dos ver. 3.30 to ver.5.00a note pc dos ver. 3.1 to ver. 5.0 note windows ver. 3.0 to ver. 3.1 note ms-dos versions 5.00 and 5.00a and pc dos ver. 5.0 are provided with a task swap function. this function, however, cannot be used in these software packages.
35 m pd17p709 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconduc- tor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
36 m pd17p709 caution this product contains an i 2 c bus interface circuit. when using the i 2 c bus interface, notify its use to nec when ordering custom code. nec can guarantee the following only when the customer informs nec of the use of the interface: purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. [memo]
37 m pd17p709 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 j96. 8
m pd17p709 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. simplehost is a trademark of nec corporation. ms-dos and windows are trademarks of microsoft corporation. pc/at and pc dos are trademarks of ibm corporation. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

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